1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and the semiconductor device, in which a low dielectric constant insulating film is used.
2. Description of the Related Art
With high integration and high speed operation of the semiconductor device, reduction of a capacitance between wirings is strongly required. In order to reduce such a parasitic capacitance, it is absolutely necessary to develop a technique of reducing the resistance of a metal wiring layer and a technique of reducing the dielectric constant of an interlayer insulating film.
Problems associated with the latter technique of reducing the dielectric constant of the interlayer insulating film will be described here. An SiO2 film produced by a plasma CVD process or an FSG (Fluorinated Silicate Glass) film is known as the interlayer insulating film. However, these insulating films have limitation to reduce the dielectric constant from a viewpoint of stability of film quality. Specifically, the dielectric constant (k) can be reduced only up to about 3.3.
In order to reduce the dielectric constant not more than 3.0, the insulating film called a low-k film is investigated. An organic silicon oxide film containing CH3 or a CF series film is known as the low-k film.
However, there is the following problem in such kind of low-k film. FIGS. 4A to 4C are sectional views of processes for illustrating the problems. The problem is generated in a process of removing a photoresist pattern in a damascene process.
In FIG. 4, for example an organic silicon oxide film (low-k film) 82 containing CH3 is formed on a silicon substrate 81 in which a semiconductor element, a Cu wiring layer and the like are provided, and a capping layer 83 is formed thereon. The capping layer 83 is formed by using the insulating film such as, for example, an SiO2 film and an SiN film.
As shown in FIG. 4B, after a photoresist pattern 84 is formed on the cap layer 83, the low-k film 82 is etched to form a wiring groove 85, using the photoresist pattern 84 as a mask.
Thereafter, as shown in FIG. 4C, the photoresist pattern 84 is removed by ashing which adopts oxygen plasma processing.
At this point, an inside wall of the wiring groove 85, which is an exposed surface of the low-k film 82, is altered by oxygen radical in plasma to produce an altered or degenerated layer 86 therein. Specifically, CH3 is drawn from the organic silicon oxide film which is exposed to the inside wall (bottom surface and side surface) of the wiring groove 85, and the inside wall of the wiring groove 85 is altered to a silicon oxide film (altered layer 86). The presence of the altered layer 86 changes a substantial k value of the low-k film 82.
The k value of the usual silicon oxide film is around 4, but the silicon oxide film (altered layer 86), in which the inside wall of the wiring groove 85 is altered, is changed to a porous silicon oxide film, so that the k value of the porous silicon oxide film is lower than that of the usual silicon oxide film.
However, actually since the porous silicon oxide film absorbs moisture, the k value of the low-k film 82 is substantially increased when the altered layer 86 is generated. Consequently, it is difficult to reduce the dielectric constant of the interlayer insulating film.
In order to solve the above-described problem, a method is tried for removing the moisture in the porous silicon oxide film which is the altered film 86. However, the method is not the effective solution, because it is difficult to remove the moisture under the present conditions.
Therefore, the ashing conditions is being reconsidered such that the altered layer 86 of the low-k film 82 becomes minimum, but the altered layer 86 still remains to an extent of about 20 nm, so that it is impossible to restrain the substantial increase in the k value of the low-k film 82. The increase in the k value becomes larger problem, as the fine device structure is advanced and the integration density is increased to narrow a distance between wirings. That is to say, as shown in FIG. 5, when the dielectric constant of the altered layer 86 becomes larger and the distance between wirings is narrowed as small as 0.1 μm, a parasitic capacitance C between adjacent conductors 87 is not negligible.